Advances in fabrication techniques and other areas of integrated circuit technology continue to decrease the size of on-chip memory. Consequently, designers are taking advantage of a rapid increase in the packing density of memory cells. Accordingly, as much as 10–20 Mbits of memory may presently be formed on a single chip and there is every reason to believe the amount of memory will continue to increase.
Although generally a positive development, the increased packing density of memory cells, and increasing memory capacity resulting therefrom, is accompanied by increased testing time and corresponding costs. For example, quality control standards often mandate that most if not all of the memory cells in a particular manufacturing lot or chip be tested. As such, the increased packing density generally increases the length and costs of the testing phase of manufacturing for each chip fabricated.
For example, an important part of quality control in the manufacture of on-chip memory is data retention testing, which determines the ability of memory cells to retain their data content over a relatively long period of time. The inability of memory cells to retain data may point to a manufacturing defect. Existing data retention testing techniques typically include writing data to a memory cell or group and subsequently reading the memory after a predetermined waiting period. The waiting period is generally much longer than memory access times for an effective test. For example, the waiting period typically ranges between about 500 ms and about 1 second, whereas read and write speeds can be performed at speeds ranging, for example, between about 20 and about 50 MHz. It follows that the increase in the number of memory cells on a chip can increase the time and corresponding costs required for data retention testing of all or a portion of the memory cells.
Accordingly, in an effort to keep the total test time to a minimum, existing data retention testing techniques typically include simultaneously writing to all of the memory cells on a chip, simultaneously holding all of the cells in one waiting period, and simultaneously reading data from all of the cells for comparison to expected values. By holding all of the memory cells on a chip in the waiting period simultaneously, only one waiting period is required for testing of each chip, thereby minimizing the total testing time. However, the simultaneous access of the large number of memory cells presents issues of power consumption management during testing, as described below.
One such power management issue regards peak power. That is, the simultaneous access of a large number of cells requires a significant demand on current and power during a short time period, which can damage chip components not necessarily designed for such increased current and power levels. Another power management issue regards average power. Generally, the average power consumption during existing memory testing techniques may be greater than desired, which can cause thermal degradation of various components and power supply voltage drop problems. Further, designing the chip to handle such peak and average power issues during testing may consume unnecessary resources on the chip since these issues may rarely, if ever, arise during normal operation.
One attempt at overcoming these power management issues has been to partition the memory being tested such that only portions of the memory cells on a chip are written to or read from at a time. In such an arrangement, data is written to a group of memory cells, the conventional waiting period is performed, data is read from the cells, and the process is repeated for each remaining group of cells. While such an approach may mitigate the power management issues discussed above, it requires the inclusion of a waiting period for each group of cells that are tested, thereby increasing the total test time required to effectively verify the data retention capabilities of all of the memory cells on a chip. As discussed above, it is desirable that this total test time be minimized to streamline fabrication and reduce costs.
Consequently, there is a need in the art to address these competing interests in effectively managing power consumption and minimizing total testing time and costs.